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Fabrication Schedule

To apply for Peer-Reviewed Subsidized Pricing, please click a date in the calendar to access an application.
 For Canadian Academic Pricing, not subject to Peer Review, please contact 
fab@cmc.ca.

Notes:
Cancelled runs are listed in red
Other technologies are available subject to demand.  Please see table at bottom of Fab Schedule for these technologies.
 
Please contact fab@cmc.ca for more information.
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TechnologyDescription
CMOSP8C/Standard (TeledyneDALSA)0.8-micron 2.7V-5.5V mixed-signal CMOS;
Double poly; Triple metal; Hi-res poly option [10kOhms/sq];
Twin-tub process on N-type or P-type wafers
Average Cycle Time:  27 Weeks
CMOSP8G/HighVoltage (TeledyneDALSA)0.8-micron 5V mixed-signal; CMOS 40-300V DMOS and PMOS transistors; 5V CMOS isolated from
40-300V CMOS; PNP bipolar and isolated NPN bipolar; Dual gate oxide technology; Hi-res poly option
[5kOhms/sq]; double poly capacitors; triple metal with TiN barrier; P-type epitaxy over p+ substrate
Average Cycle Time:  27 Weeks
IMEC SOIIMEC Standard SiPhotonics
Sensonit/ (Micronit)Sensonit: customized depth microchannels and integrated electrodes on glass substrates
with optional ITO in-channel electrode or back side metal electrode
Average Cycle Time:  12 Weeks
UW-MEMS/ (CIRFE)Two gold layers surface micromaching process on alumina substrate
Turnaround time: TBA
NanoSOINanopatterning of metal and silicon using e-beam litho. Process conducted on SOI with optional oxide etch.
Average turnaround time is 9 weeks.
LTCC LTCC Process includes 6 layers of Du Pont 9K7. 
The process contains 7 conductor layers: 6 silver-based layers with solderable top and
bottom layers. There is an extra gold-based layer on the top side for wirebonding. 
Design blocks are: 3cm x 3cm, 3cm x 6cm or 6cm x 6cm.
Estimated delivery time is: 2 months
FlowJEMQuick turnaround, cost effective rigid polymer fabrication technology
for microfluidic devices
GaN 150/ (CPFC)GaN-based HFET technology fabricated on 3-in. silicon carbide wafers of 75 µm thickness.
It features a 0.15 µm long metal gate, two metal layers (1ME and 2ME) for interconnect, Through-Wafer
Vias (TWVs), 50 O/sq nichrome resistors and MIM capacitors of 0.19 fF/µm2.
The process is suitable for 30 V maximum drain voltage bias, and yields power
levels of ~7 W/mm (measured at 8 GHz).

 
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